 FPGA clock speed, Base clock of FPGA |
|
|
|
|
Related links
Visit our LabVIEW Wiki LabVIEW Embedded Portal
Tags |
(This content has not been tagged yet)
|
 ·
 ·
 ·
 ·
 ·
 ·
 ·
 ·
 ·
 ·
 ·
 ·
 |
 Nov 12 2007, 02:58 PM
Post
#1
|
|||
|
Active  Member Posts: 20 Joined: 8-June 06 Member No.: 5265 LV:8.0.1 ,8.0.1 ,8.0.1 
 |
Hello ,
I am working on cRIO and wish to know this about FPGA. What is the base clock of a FPGA chip( 40 MHz or 200 MHz). If 40 MHz is base clock then how is 200 MHz derived from it. ( I mean ho we divide one clock tick into 5) Awaiting a response. Thanks
|
||
 |
 
|
||
| Ad |
Nov 12 2007, 02:58 PM
Post
#
|
||
|
|
|
||
|
|
|
||
|
Nov 13 2007, 03:21 PM
Post
#2
|
|||
|
4 more posts to go! Member Posts: 6 Joined: 9-April 07 Member No.: 8318 Using LabVIEW Since:1998 LV:8.5 ,. ,. 
|
QUOTE (vronto31 @ Nov 12 2007, 10:58 AM)  Hello , I am working on cRIO and wish to know this about FPGA. What is the base clock of a FPGA chip( 40 MHz or 200 MHz). If 40 MHz is base clock then how is 200 MHz derived from it. ( I mean ho we divide one clock tick into 5) Awaiting a response. Thanks The base clock is 40 MHz. Other clock frequencies (2.5 - 210 MHz) can be generated via PLL in the FPGA. Clock options are (40 x num / denom) within the afore mentioned range, where num and denom are integers between 1 and 32.
|
||
|
|
|
||
|
| Time is now: 8th January 2009 - 11:55 PM |