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> Deploy issues with cRIO 9012, Deploying to the 9012 always comes up with an error about the top VI
JodyK
post May 1 2007, 03:29 PM
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Joined: 11-April 07
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Member No.: 8335
Using LabVIEW Since:2006
LV:8.20 ,8.0.1 ,7.1.1
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This is a strange issue from a debug sense.

I've been developing a cRIO (9012) application and am pretty far along in development. I was at a customer's site developing with the cRIO in the full system loop and everything was fine. Running the system in targetted mode with no issues. Anyways I moved off the actual system and did 2 or 3 hours of developing in a conference room. Mostly code that handles USB and file management. When I went back to the system to test the new code, it wouldn't deploy. I have included the error below.

...Other Deploys...
Deploying NI_FileType.lvlib:Get File Type.vi (15.73 K)
Deploying Check if File or Folder Exists.vi (7.26 K)
Deploying nirviCommon.vi (38.10 K)
Deploying nirviCommon.vi (already deployed)
Deploying Instance 2 23EscapeDataLogging(Host) .vi
Deploying Instance 1 23EscapeDataLogging(Host) .vi
Deploying EscapeDataLogging(Host).vi
Failed to download EscapeDataLogging(Host).vi
LabVIEW: The VI is not in memory.
LabVIEW: The VI is not in memory.


EscapeDataLogging(Host) is the top level VI. I think that "instance" thing might be a little weird, but honestly I didn't pay that much attention to successful deploys.

Other info:
I recently upgraded to LabVIEW 8.2.1
I seem to still be able to deploy VIs that do not include FPGA code
Deploying a known-good VI (one that I used early on to capture raw data but have not modified since) failed
I upgraded all the appropriate modules from the latest development CDs - Real-time, FPGA, niRIO, Device Drivers
I reloaded the latest modules onto the cRIO itself


Anyone got some thoughts on this?


Jody


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post May 1 2007, 03:29 PM
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JodyK
post May 1 2007, 04:34 PM
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Posts: 9
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Member No.: 8335
Using LabVIEW Since:2006
LV:8.20 ,8.0.1 ,7.1.1
United States Nothing Selected Nothing Selected


The issue seems to have been fixed after recompiling my FPGA code. My best guess is some update along the way changed how the FPGA and RTOS VI interact but since a bitstream had already been generated it didn't prompt me for a new fpga compile. Anyways issue fixed. I'll leave these posts up in case anyone else has issues.

-Jody


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