hi

I'm building a set of FPGA subVIs for use in our future cRIO applications. The subVIs will be of type "8 channel DO", "8 channel DI", "8 channel PWM" et.c, with an array as input.

I want the user to be able to place a subVI on the block diagram, connect an input, open the front panel of the subVI and select which 8 channels to use (from an I/O name control).
This is not a problem to implement, but what about using multiple instances of the same VI? All subVIs point to the same file and hence changes to one equals changes to all.

Is there a way around this, to be able to save changes made to every subVI placed on the block diagram independently?

/Emil

This screams Express VIs. Norm Kirchner say they aren't that hard to program, so good luck!

Ton

Thank you. I was afraid that would be the case.
Do you know if there are limitations when creating Express VIs for the FPGA-palette?

I'm just catching up on some older messages.

Another possible solution to this problem is to use I/O references (new in LabVIEW FPGA) in the subVI and specify the I/O channel as constants in the calling VI. The subVI does not need to change and the user can specify the specific I/O in a clear readable fashion. You cannot put the I/O references into an array to pass to the subVI, but you can bundle them in a cluster. I have attached a very simple example for 8 DI channels.

For the "Use 8 Channels", how do I use it? When I try to compile it, it says channel not found. When I actually assign a channel to it, the wire between the cluster and subVI becomes broken.

You should first create a new project and configure your FPGA target and all of the I/O for your target that you plan to use. Then add the two VIs to the FPGA target. Open up the Use 8 Channels and help it find the subVI if necessary.

Then if you go to the diagram you should be able to click on the I/O references and select any of the channels you have configured in the project for your FPGA target.

Yea, I did all of those. The strange part is that when I click on the I/O references, it says "No I/O Available". I am very sure I have configured the I/O for my target correctly.

What I/O modules and channels have you configured? Can you attach a screen shot of the project with the configuration or the project file.

Make sure the VIs are assigned to the same FPGA target in the project.

This post has been edited by LV_FPGA_SE: Sep 10 2008, 08:13 PM

The folders saying Connector 0, 1, etc have the I/Os in them.

It turns out the IO references are somewhat specific to the type of IO device. My original VI was created for cRIO IO. I updated the example for R series and have attached the new VIs and project.

Thanks. Let's give it a try.